(1) Field of the Invention
The invention relates to integrated circuit devices, and more particularly, to a method to monitor isolation integrity of the floating gate in the manufacture of a nonvolatile memory device.
(2) Description of the Prior Art
Memory devices are an important building block in the art of integrated circuit design and manufacture. Memory devices are used for temporary and permanent data storage in the integrated circuit or system. For example, a random access memory, or RAM, can be used to temporarily store data values. RAM memories are formed in static or dynamic forms. In either case, RAM requires a continuous power supply in order to retain the data. Once power is removed, the RAM cell discharges and the data value is lost. In read-only memory, or ROM, data is permanently stored. Removal of the power supply doesn't erase the data state. Nonvolatile programmable memory devices, such as electrically erasable programmable ROM, or EEPROM, also maintain the data state in the absence of the power supply. However, EEPROM also adds the ability to program and re-program the data state values.
A popular form of EEPROM in the art is the flash EEPROM. In the flash EEPROM, a block of the memory array may be erased simultaneously. Typically, such flash EEPROM devices are MOSFET devices formed with a complex gate comprising a control electrode and a floating electrode. Referring now to FIG. 14, a cross section of a portion of an exemplary flash EEPROM memory array is illustrated. In this example, two flash transistors are formed around a common source region 50. In practice, a large array of these devices, or cells, are formed together in a memory chip. The devices are formed on a substrate 10. Each device comprises a floating gate and control gate. The floating gate comprises a floating gate conductor layer 22 overlying the substrate 10 with a floating gate oxide layer 18 therebetween. The control gate comprises a control gate conductor layer 90 overlying the substrate 10 with a control gate oxide layer 98 therebetween. In addition, a dielectric layer 96 is formed between the control gate conductor layer 90 and the floating gate conductor layer 22 to separate and to electrically isolate the floating and control gates. The flash transistors further comprise source regions 50 in the substrate. Here, the source region is a common source or source line. In addition, drain regions 92, or bit lines, are formed in the substrate 10. The exemplary flash transistors are split-gate devices. Split-gate devices are formed such the device channel between the drain regions 92 and the source regions 50 is controlled by two, distinct regions. In a first region, the control gate 90 directly overlies the substrate 10. In a second region, the floating gate 22 directly overlies the substrate 10.
In the flash device, the voltage threshold of the complex-gated MOSFET is controlled by charge storage on the floating gate 22. If the flash device is formed on a p-type substrate 10, then the resulting device is an NMOS transistor. This NMOS transistor will be turned ON when the control gate 22 voltage is forced to a value above the threshold voltage required to invert the p-type substrate 10 between the drain 92 and source 50 and to thereby create an n-channel region. In this case, a positive voltage must be forced onto the control gate 90 to invert the channel. In the first region, where the control gate 90 is directly over the substrate 10, inversion occurs as in a standard MOS device. However, in the second region, where the floating gate 22 directly overlies the substrate 10, the control gate voltage is divide by the series capacitance of the floating gate 22. Therefore, a larger control gate voltage is required to create the channel under the floating gate 22.
In addition to the capacitive effect, the threshold voltage of the flash device varies directly with the stored charge on the floating gate 22. For example, if a negative charge is stored on the floating gate 22, then the threshold voltage is increased due to the need to compensate for the negative charge prior to creating the channel. Conversely, positive charge on the floating gate 22 will decrease the threshold voltage. This effect is used in the flash device as a means of storing the data state. The device is erased or is programmed by either removing charge from or storing charge onto the floating gate 22. There are several mechanisms for moving charge onto or off from the floating gate 22. Each involves raising the energy of the electrons such that they cross one of the dielectric layers 18 and 96. For example, electrons may move from the source region 50 or from the substrate 10 onto the floating gate 22 during a programming operation. Electrons may move from the floating gate 22 to the control gate 90 during an erasing operation.
Once the floating gate 22 is charged/discharged, the flash device is designed to store that state indefinitely. Since the floating gate conductor layer 22 is not connected to any other conductor layer, the charge state of the floating gate 22 should, under ideal conditions, be maintained indefinitely. However, the charge storage capability may be compromised. If the floating gate oxide layer 18 is damaged or is otherwise incorrectly formed, then charge leakage paths 115 and 120 may be formed between the floating gate 22 and the substrate 10 or the source region 50. If the dielectric layer 38 between the floating gate 22 and the source plug layer 54 is defective, then charge can leak through this isolation interface 125.
In those cases where any of the dielectric layers surrounding the floating gate 22 is defective, then the floating gate 22 may be effectively shorted to the conductive layer on the other side of that defective dielectric. This condition is called a “stuck” condition. In this case, the floating gate 22 is typically described as “stuck” to the source 50 or to the substrate 10. In the art of integrated circuit testing, circuit nodes within the design are modeled as “stuck at” ‘0’ or ‘1’ for purposes of grading the comprehensiveness of the testing input signal pattern. A comprehensive testing pattern will detect all or nearly all possible circuit node “stuck at” conditions. The testing of nonvolatile memory arrays presents a unique testing problem because each cell in the array will need to be erased, programmed, and then read in each possible state (0 and 1). In addition, patterns of data have to be written to blocks of cells to detect inter-cell defects.
This functional testing regime is performed after all of the wafer-level processing for the integrated circuit is performed. In a typical product, between about 25 and 30 masking levels are used to process the complete sequence. The complete manufacturing process flow is therefore expensive and time consuming. If individual bit failures are detected at a low rate in the final wafer test, then it is possible to re-configure the product, through redundant circuits and cells formed on the IC, such that a functional memory device is still achieved. However, if a larger problem occurs such that redundancy is not sufficient to fix the problem, then the circuits are scrapped. A wafer-wide problem may cause the entire wafer to be scrapped and thereby result in a loss of the entire processing investment. It is found that a significant cause for such scrap is the integrity or quality of the dielectric isolation surrounding the floating gates. It is a central object of the present invention to provide a method to detect quality problems with this floating gate isolation early in the process flow so that the cost of scrapped wafers is reduced.
Several prior art inventions relate to methods to detect circuit faults in nonvolatile memory circuits. U.S. Pat. No. 5,606,527 to Kwack et al describes methods to detect short circuits between signal lines in a nonvolatile memory circuit. Testing circuits are added to create a test mode to check for shorts on the product memory device. U.S. Pat. No. 6,064,608 to Ikeda describes a method and a structure to test for short circuits between bit line and wordlines in a nonvolatile memory device. U.S. Pat. No. 5,343,431 to Ohtsuka et al describes a method and a circuit to detect bit line-to-bit line shorts in a nonvolatile memory device.